1. Field of the Invention
The present invention relates to a flat display panel technology, and more particularly, to a pixel array structure and a method for driving a flat display panel thereof.
2. Description of Related Art
In the presence of all structures of the flat display panel, one species is so-called the half source driving (hereinafter “HSD”) structure. The HSD structure would reduce the number of the data lines to half by increasing the number of the scan lines to double. Since the number of the data lines is reduced to half, the fabricating cost of the source driver would be relatively reduced.
FIG. 1 illustrates a partial schematic view of a flat display panel 100 of a conventional HSD structure. FIG. 2 illustrates a partial driving time chart of the flat display panel 100 applying a panel driving technique of two line two dot inversion. Referring to FIG. 1 and FIG. 2 simultaneously, the flat display panel 100 has a plurality of pixels Pix arranged in an array. The pixels Pix which are marked with notations R1, G1, B1, R2, G2, B2 are located within a display area AA of the flat display panel 100. On the other hand, the pixels Pix that are not marked with the notations R1, G1, B1, R2, G2, B2 are dummy pixels and located in the periphery of the display area AA.
Moreover, notations S1˜S4 are data lines; a notation Sdum is a dummy data line; notations G1˜G9 are scan lines; and a notation Gdum is a dummy scan line. The driving time chart disclosed in FIG. 2 includes control signals LD, POL, STVD, OE1˜OE3 and a timing signal CLK provided by a timing controller, and a display data SD provided by a source driver. Here, the control signals LD and POL are configured to control the source driver and the control signals STVD and OE1˜OE3 are configured to control a gate driver.
It is shown in FIG. 2 that the timing controller must provide the control signals STVD and OE1˜OE3 which lead to more complicated operations, so that the gate driver manufactured on a Y-board (not shown) transmits scan signals SS respectively to the scan lines G1˜G9. Moreover, by providing corresponding control signals LD and POL, the source driver manufactured on an X-board (not shown) can follow dashed arrows in FIG. 1 in an order of {circle around (1)} {circle around (2)} {circle around (3)} {circle around (4)} and write the corresponding display data SD into each pixel Pix.
In light of the foregoing, even though the flat display panel 100 illustrated in FIG. 1 reduces the number of data lines by half and consequently reduces the fabricating cost of the source driver, it is observed from the driving time chart disclosed in FIG. 2 that methods of the timing controller to control the gate driver and the source driver are complicated, and the timing controller must be additionally disposed with at least three line buffers that are different from those used when normally driving the panel (which is because the source driver includes three pixel rows by following the dashed arrows in FIG. 1 and travel in an order of {circle around (1)} {circle around (2)} {circle around (3)} {circle around (4)}) so as to temporarily store the display data SD required by every three pixel rows respectively. Furthermore, in order to correspond to this driving method, a gate driver with complicated circuit structure must be fabricated on the Y-board, so that the overall fabricating price of the gate driver is dramatically increased.